Frequency multiplier circuits, such as frequency doubler circuits, are useful for multiplying the frequency of an input signal. Such circuits are useful, for example, for modifying the frequency of an input sequence of pulses (clock pulse sequence) which is used to control the ON vs. OFF timing (control timing) of various transistors in an integrated circuit.
Among the kinds of multiplying circuits in the prior art are analog or digital circuits containing phase-locked loops. However, in order to achieve high accuracy of frequency multiplication, the phase-locked loop circuit approach requires signal stability which, in turn results in relatively long circuit settling times--viz., many periods of the input (clock) signal after its commencement until the output becomes a steady and accurate representation of the desired output signal. Thus, this approach wastes valuable time when the input signal initially is applied to the circuit. In addition, because of these long settling times, the phase-locked loop approach requires the use of relatively high capacitance and/or resistance elements which cannot easily if at all be fabricated as an integrated part of an integrated circuit at the surface of a semiconductor body ("chip"). Instead, these elements must ordinarily be formed external to the chip--that is to say, forming a so-called "hybrid" integrated circuit. Such a hybrid circuit is described, for example, in the paper "An Integrated PLL Clock Generator for 275 MHz Graphic Displays" by G. Gutierrez et al published in IEEE 1990 Custom Integrated Circuits Conference , pp. 15.1.1-15.1.4 (1990). The circuit described in detail in that paper utilized two external resistors and two external capacitors.
It would therefore be desirable to have a frequency multiplier circuit which does not have such long settling times and does not require any external resistors or capacitors or other external components, in order to reduce circuit costs and complexity.